1. Field of the Invention
The present invention relates to a liquid crystal display device and more particularly, to an array substrate for a liquid crystal display device and a method of manufacturing the same.
2. Discussion of the Related Art
A liquid crystal display (LCD) device includes an upper substrate, a lower substrate and a liquid crystal layer disposed between the upper and lower substrates. The LCD device uses an optical anisotropy of liquid crystal to produce an image. An electric field is used to control the light transmittance of the liquid crystal layer by varying the arrangement of liquid crystal molecules.
One substrate of the LCD device includes a thin film transistor that acts as a switching element. An LCD device, which includes the thin film transistor, is referred to as an active matrix liquid crystal display (AMLCD) device and it has a high resolution and can display an excellent moving image. Hydrogenated amorphous silicon (a-Si:H) is widely used as an active layer of the thin film transistor because the hydrogenated amorphous silicon can be formed on a large, low cost substrate such as glass.
However, the hydrogenated amorphous silicon includes weak Si—Si bonds and dangling bonds due to disordered atomic arrangement. Thus, when light or an electric field is applied, there may be stability problems in the hydrogenated amorphous silicon used as the active layer of the thin film transistor. Additionally, the thin film transistor including the hydrogenated amorphous silicon has a low field effect mobility of about 0.1 to 1.0 cm2/V·s and is difficult to be used for a driver integrated circuit (driver IC) that controls the thin film transistor. The driver IC usually includes CMOS (complementary metal-oxide-semiconductor) transistors that require crystalline silicon as active layers. Because of this, the driver IC is usually connected to the array substrate using a TAB (tape automated bonding) system. This adds significant cost to the LCD device.
To avoid the limitations of amorphous silicon, LCD devices incorporating polycrystalline silicon as an active layer are being researched and developed. Polycrystalline silicon is highly beneficial because it is much better suited for use in the driver IC than amorphous silicon. Thus, polycrystalline silicon has the advantage that the number of fabrication steps could be reduced because a thin film transistor and a driver IC could be formed on the same substrate, eliminating the need for TAB bonding. Furthermore, the field effect mobility of polycrystalline silicon is 100 to 200 times greater than that of amorphous silicon. Polycrystalline silicon is also optically and thermally stable.
FIG. 1 is a schematic view showing an array substrate of a liquid crystal display device having driver integrated circuits (driver ICs) according to the related art. Referring to FIG. 1, the array substrate includes a display region D1 and a non-display region D2 on an insulating substrate 10. In the display region D1, gate lines GL are formed along a first direction, and data lines DL are formed along a second direction perpendicular to the first direction. The gate lines GL and the data lines DL cross each other to define pixel regions P. The pixel regions P form a matrix. In each pixel region P, a switching element T and a pixel electrode 78, which is connected to the switching element T, are formed. In the non-display region D2, gate and data driving portions GP and DP are disposed. The gate driving portion GP is disposed in the left region of the substrate 10 in the context of the figure, and the data driving portion DP is disposed in the top region of the substrate 10 in the context of the figure. The gate driving portion GP, which includes a plurality of driver ICs, supplies an address signal to the gate lines GL, and the data driving portion DP, which also includes a plurality of driver ICs, supplies an image signal to the data lines DL.
The gate driving portion GP and the data driving portion DP are electrically connected to an outer control circuit (not shown) with signal input terminals OL which are formed on one edge of the substrate 10, so that the outer control circuit (not shown) controls the driver ICs of the gate driving portion GP and the data driving portion DP. The outer control circuit (not shown) applies signals to the gate and data driving portions GP and DP through the signal input terminals OL.
The gate driving portion GP and the data driving portion DP include driver ICs having a CMOS (complementary metal-oxide-semiconductor) transistor as an inverter which changes a direct current into an alternating current. The CMOS transistor comprises an n-channel MOS transistor (or n-type MOS transistor), in which electrons are the majority carriers, and a p-channel MOS transistor (or p-type MOS transistor), in which holes are the majority carriers. Therefore, in an n-channel MOS transistor, most of the current is carried by negatively charged electrons, and in a p-channel MOS transistor, most of the conduction is carried by positively charged holes. The thin film transistor T of the display region D1 and the CMOS transistor (not shown) of the non-display region D2 may use polycrystalline silicon as an active layer, and thus can be formed on the same substrate 10.
FIG. 2 is a plan view illustrating a pixel region of an array substrate including a polycrystalline silicon thin film transistor according to the related art. Referring to FIG. 2, a gate line GL is formed along a direction on a substrate 10, and a data line DL crosses the gate line GL to define a pixel region P. A thin film transistor T is formed at the crossing portion of the gate and data lines GL and DL. The thin film transistor T includes an active layer 18 of polycrystalline silicon, a gate electrode 34 over the active layer 18, and source and drain electrodes 70 and 72 contacting the active layer 18. A pixel electrode 78 is formed in the pixel region P and is connected to the drain electrode 72. A storage capacitor CST is also formed in the pixel region P. The storage capacitor CST includes an impurity-doped polycrystalline silicon pattern 20, as a first electrode, and a storage line 36, as a second electrode. The storage line 36 is disposed over the impurity-doped polycrystalline silicon pattern 20 and traverses the pixel region P.
FIGS. 3A and 3B are cross-sectional views of an array substrate including driver ICs according to the related art. FIG. 3A illustrates a CMOS transistor in a driving region, and FIG. 3B illustrates a pixel region including a switching element. FIG. 3B corresponds to a cross-section taken along the line III-III of FIG. 2. Referring to FIGS. 3A and 3B, a buffer layer 12 is formed on a substrate 10. A CMOS transistor is formed in a driving region including a first driving region A and a second driving region B. The CMOS transistor is composed of an n-type MOS transistor and a p-type MOS transistor in the first and second driving regions A and B, respectively. An n-type thin film transistor, as a switching element, is formed in a switching region C of a pixel region P, and a storage capacitor CST is formed in a storage region ST of the pixel region P. A pixel electrode 78 is also formed in the pixel region P and is connected to the n-type thin film transistor.
More particularly, first, second and third active patterns 14, 16 and 18 are formed in the first driving region A, the second driving region B and the switching region C, respectively. Each of the first, second and third active patterns 14, 16 and 18 is formed of polycrystalline silicon and includes an intrinsic portion V1 and doped portions V2. The first and third active patterns 14 and 18 include a lightly doped drain (LDD) portion F between the intrinsic portion V1 and each doped portion V2. The LDD portion F includes impurities of low density and prevents leakage current of an off-state, that is, applying reverse bias to a thin film transistor. An extension portion 20 extends from the third active pattern 18 into the pixel region P.
A gate insulating layer 28 is formed on the entire surface of the substrate 10 including the first, second and third active patterns 14, 16 and 18. First, second and third gate electrodes 30, 32 and 34 are formed on the gate insulating layer 28. The first, second and third gate electrodes 30, 32 and 34 correspond to the intrinsic portions of the first, second and third active patterns 14, 16 and 18, respectively. A storage line 36 traversing the pixel region P is also formed on the gate insulating layer 38. The storage line 36 is disposed over the extension portion 20. The extension portion 20 and the storage line 36 function as a first electrode and a second electrode, respectively, to form the storage capacitor CST. An inter insulating layer 48 is formed on the entire surface of the substrate 10 including the first, second and third gate electrodes 30, 32 and 34 and the storage line 36. The inter insulating layer 48 and the gate insulating layer 28 include contact holes exposing the doped portions of the first, second and third active patterns 14, 16 and 18.
First source and drain electrodes 62 and 64, second source and drain electrodes 66 and 68, and third source and drain electrodes 70 and 72 are formed on the inter insulating layer 48. The first source and drain electrodes 62 and 64 contact the exposed doped portions V2 of the first active pattern 14, the second source and drain electrodes 66 and 68 contact the exposed doped portions V2 of the second active pattern 16, and the third source and drain electrodes 70 and 72 contact the exposed doped portions V2 of the third active pattern 18. A pixel electrode 78 is formed on a passivation layer 74 in the pixel region P and is connected to the third drain electrode 72 in the switching region C. As stated above, the n-type thin film transistor in the switching region C and the CMOS transistor in the driving region are formed on the same substrate through the same processes.
A manufacturing method of an array substrate including driver ICs according to the related art will be explained hereinafter with reference to attached drawings.
FIGS. 4A and 4B to FIGS. 12A and 12B are cross-sectional views illustrating a manufacturing method of an array substrate including driver ICs according to the related art. FIGS. 4B to 12B illustrate a pixel region including a switching element and correspond to cross-sections taken along the line III-III of FIG. 2. Referring to FIGS. 4A and 4B, a driving region, which includes a first driving region A and a second driving region B, and a pixel region P, which includes a switching region C and a storage region ST, are defined on a substrate 10. A buffer layer 12 is formed on the substrate 10 by depositing silicon oxide (SiO2).
First, second and third active patterns 14, 16 and 18 are formed on the buffer layer 12 in the first driving region A, the second driving region B and the switching region C, respectively, through a first mask process. The first, second and third active patterns 14, 16 and 18 are formed of polycrystalline silicon. Each of the first, second and third active patterns 14, 16 and 18 includes an intrinsic portion V1 and doped portions V2. The first and third active patterns 14 and 18 further include a lightly doped drain (LDD) portion F between the intrinsic portion V1 and each doped portion V2. An extension portion 20 is also formed on the buffer layer 12 in the storage region ST. The extension portion 20 extends from the third active pattern 18.
In FIGS. 5A and 5B, first, second and third photoresist patterns 22, 24 and 26 are formed on the first, second and third active patterns 14, 16 and 18, respectively, by coating a photoresist material on the entire surface of the substrate 10 and then patterning the photoresist material through a second mask process. The extension portion 20 is not covered with the photoresist patterns 22, 24 and 26 and is exposed. Next, n+ or p+ ion doping is performed in the exposed extension portion 20. The doped extension portion 20 functions as an electrode for a storage capacitor. The first, second and third photoresist patterns 22, 24 and 26 are removed.
In FIGS. 6A and 6B, a gate insulating layer 28 is formed on the substrate 10 including the doped extension portion 20 by depositing an inorganic insulating material such as silicon nitride (SiNX) or silicon oxide (SiO2). First, second and third gate electrodes 30, 32 and 34 are formed on the gate insulating layer 28 by sequentially depositing and then patterning aluminum (Al) or an aluminum alloy such as AlNd through a third mask process. The first, second and third gate electrodes 30, 32 and 34 correspond to the intrinsic portions of the first, second and third active patterns 14, 16 and 18, respectively. A storage line 36 is also formed on the gate insulating layer 28 over the extension portion 20 in the storage region ST. The extension portion 20 and the storage line 36 form a storage capacitor CST and function as first and second electrodes of the storage capacitor CST, respectively. Subsequently, n− ion doping, in which n-type impurities are lightly doped, is carried out on the entire surface of the substrate 10 including the first, second and third gate electrodes 30, 32 and 34. Thus, n-type ions are lightly doped in the LDD portions F of the first and third active patterns 14 and 18 and the doped portions V2 of the first, second and third active patterns 14, 16 and 18.
In FIGS. 7A and 7B, a photoresist material is coated on the entire surface of the substrate 10 where n− ion doping is performed and then is patterned through a fourth mask process, to thereby form fourth, fifth and sixth photoresist patterns 38, 40 and 42. The fourth photoresist pattern 38 covers the first gate electrode 30 and the LDD portions F of the first active pattern 14. The fifth photoresist pattern 40 covers the second gate electrode 32 and the second active pattern 16. The sixth photoresist pattern 42 covers the third gate electrode 34 and the LDD portions F of the third active pattern 18. Here, the doped portions V2 of the first and third active patterns 14 and 18 are exposed. Next, n+ ion doping is performed on the entire surface of the substrate 10 including the fourth, fifth and sixth photoresist patterns 38, 40 and 42. Therefore, n-type ions are heavily doped in the doped portions V2 of the first and third active patterns 14 and 18. The fourth, fifth and sixth photoresist patterns 38, 40 and 42 are then removed.
In FIGS. 8A and 8B, a photoresist material is coated on the substrate 10 where n+ ion doping is performed. Then, the photoresist material is patterned through a fifth mask process, to thereby form seventh and eighth photoresist patterns 44 and 46. The seventh photoresist pattern 44 covers the first gate electrode 30 and the first active pattern 14, and the eighth photoresist pattern 46 covers the third gate electrode 34 and the third active pattern 18. The eighth photoresist pattern 46 also covers the storage line 36. Subsequently, p+ ion doping is performed on the entire surface of the substrate 10 including the seventh and eighth photoresist patterns 44 and 46, and p-type ions are heavily doped in the doped portions V2 of the second active pattern 16. The seventh and eighth photoresist patterns 44 and 46 are then removed.
In FIGS. 9A and 9B, an inter insulating layer 48 is formed on the entire surface of the substrate 10 where p+ ion doping is performed. The inter insulating layer 48 is patterned through a sixth mask process to form first, second, third, fourth, fifth and sixth contact holes 50, 52, 54, 56, 58 and 60. The first and second contact holes 50 and 52 expose the doped portions V2 of the first active pattern 14, the third and fourth contact holes 54 and 56 expose the doped portions V2 of the second active pattern 16, and the fifth and sixth contact holes 58 and 60 expose the doped portions V2 of the third active pattern 18. The inter insulating layer 48 is formed of silicon oxide (SiO2).
In FIGS. 10A and 10B, first source and drain electrodes 62 and 64, second source and drain electrodes 66 and 68, and third source and drain electrodes 70 and 72 are formed on the inter insulating layer 48 by sequentially depositing and then patterning a metallic material mentioned above through a seventh mask process. The first source and drain electrodes 62 and 64 contact the doped portions V2 of the first active pattern 14 through the first and second contact holes 50 and 52. The second source and drain electrodes 66 and 68 contact the doped portions V2 of the second active pattern 16 through the third and fourth contact holes 54 and 56. The third source and drain electrodes 70 and 72 contact the doped portions V2 of the third active pattern 18 through the fifth and sixth contact holes 58 and 60.
In FIGS. 11A and 11B, a passivation layer 74 is formed on the entire surface of the substrate 10 including the source electrodes 62, 66 and 70 and the drain electrodes 64, 68 and 72 thereon. The passivation layer 74 is patterned through an eighth mask process to thereby form a drain contact hole 76. The drain contact hole 76 exposes the third drain electrode 72 in the switching region C.
In FIGS. 12A and 12B, a pixel electrode 78 is formed on the passivation layer 74 in the pixel region P by sequentially depositing and patterning a transparent conductive material through a ninth mask process. The pixel electrode 78 contacts the third drain electrode 72 through the drain contact hole 76.
The array substrate of the related art may be fabricated through the above-mentioned mask processes. However, problems may frequently occur because the related art array substrate is fabricated through a large number of mask processes, each mask process including several steps, such as cleaning, coating a photoresist layer, exposing through a mask, developing the photoresist layer, and etching. In addition, manufacturing time and costs are increased, and productivity of the processes is lowered.